View NAND04GR3B2DZL1F_6760103.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary data this is preliminary information on a new product now in deve lopment or undergoing evaluation. details are subject to change without notice. september 2007 rev 2 1/69 1 nand04g-b2d, nand08g-bxc 4 gbit, 8 gbit, 2112 byte/1056 word page multiplane architecture, 1.8 v or 3 v, nand flash memories features high density nand flash memory ? up to 8 gbit memory array ? cost-effective solution for mass storage applications nand interface ? x8 or 16x bus width ? multiplexed address/data supply voltage: 1.8 v or 3.0 v device page size ? x8 device: (2048 + 64 spare) bytes ? x16 device: (1024 + 32 spare) words block size ? x8 device: (128k + 4 k spare) bytes ? x16 device: (64k + 2 k spare) words multiplane architecture ? array split into two independent planes ? program/erase operations can be performed on both planes at the same time page read/program ? random access: 25 s (max) ? sequential access: 25 ns (min) ? page program time: 200 s (typ) ? multiplane page program time (2 pages): 200 s (typ) copy back program with automatic error detection code (edc) cache read mode fast block erase ? block erase time: 1.5 ms (typ) ? multiblock erase time (2 blocks): 1.5 ms (typ) status register electronic signature chip enable ?don?t care? serial number option r data protection: ? hardware program/erase disabled during power transitions ? non-volatile protection option onfi 1.0 compliant command set data integrity ? 100 000 program/erase cycles (with ecc (error correction code)) ? 10 years data retention ecopack ? packages table 1. device summary reference part number nand04g-b2d nand04gr3b2d nand04gw3b2d nand04gr4b2d (1) nand04gw4b2d (1) 1. x16 organization only avai lable for mcp products. nand08g-bxc nand08gr3b2c, nand08gw3b2c nand08gr4b2c (1) nand08gw4b2c (1) nand08gr3b4c nand08gw3b4c lga tsop48 12 x 20 mm (n) lga52 12 x 17 mm (zl) www.st.com
contents nand04g-b2d, nand08g-bxc 2/69 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2 memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3 signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.1 inputs/outputs (i/o0-i/o7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.2 inputs/outputs (i/o8-i/o15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.3 address latch enable (al) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.4 command latch enable (cl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.5 chip enable (e) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.6 read enable (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.7 write enable (w) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.8 write protect (wp) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.9 ready/busy (rb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.10 v dd supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 3.11 v ss ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4 bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.1 command input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.2 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.3 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.4 data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.5 write protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.6 standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 5 command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6 device operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1 read memory array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.1 random read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.1.2 page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.2 cache read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
nand04g-b2d, nand0 8g-bxc contents 3/69 6.3 page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.1 sequential input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.3.2 random data input in page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6.4 multiplane page program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 6.5 copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6.6 multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6.7 block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 6.8 multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.9 error detection code (edc) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 6.10 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 6.11 read status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11.1 write protection bit (sr7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11.2 p/e/r controller and cache ready/busy bit (sr6) . . . . . . . . . . . . . . . . . 34 6.11.3 p/e/r controller bit (sr5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11.4 error bit (sr0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 6.11.5 sr4, sr3, sr2 and sr1 are reserved . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.12 read status enhanced . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.13 read edc status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 6.14 read electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 6.15 read onfi signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 6.16 read parameter page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 7 concurrent operations and ex tended read status . . . . . . . . . . . . . . . . 43 8 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 software algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 bad block management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.2 nand flash memory failure modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.4 wear-leveling algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.5 error correction code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 10 program and erase times and endurance cycles . . . . . . . . . . . . . . . . . 48
contents nand04g-b2d, nand08g-bxc 4/69 11 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 12 dc and ac parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 12.1 ready/busy signal electrical characteristics . . . . . . . . . . . . . . . . . . . . . . 63 12.2 data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 13 package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 14 part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 15 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
nand04g-b2d, nand08g-bxc list of tables 5/69 list of tables table 1. device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 table 2. product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 3. signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 table 4. valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 5. bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 6. address insertion (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 table 7. address insertion (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 8. address definition (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 9. address definition (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 table 10. commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 11. copy back program addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 table 12. address definition for edc units (x8 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 13. address definition for edc units (x16 devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 14. status register bits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 table 15. edc status register bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 table 16. electronic signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 17. electronic signature byte 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 table 18. electronic signature byte 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 19. electronic signature byte 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 table 20. read onfi signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 table 21. parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 22. extended read status register commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 table 23. block failure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 table 24. program erase times and prog ram erase endurance cycles . . . . . . . . . . . . . . . . . . . . . . . 48 table 25. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 26. operating and ac measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 27. capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 28. dc characteristics (1.8 v devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 29. dc characteristics (3 v devices). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 30. ac characteristics for command, address, data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 table 31. ac characteristics for operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 table 32. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data. . . . . 65 table 33. lga52 12 x 17 mm, 1 mm pitch, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . 66 table 34. ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 table 35. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
list of figures nand04g-b2d, nand08g-bxc 6/69 list of figures figure 1. logic block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 2. logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 3. tsop48 connections for nand04g-b2d and nand08g-bxc . . . . . . . . . . . . . . . . . . . . . 11 figure 4. lga52 connections for nand04g-b2d and nand08g-b2c devices. . . . . . . . . . . . . . . . 12 figure 5. lga52 connections for the nand08g-b4c devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 6. memory array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 7. read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 8. random data output during sequential data output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 9. cache read (sequential) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 10. cache read (random) operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 11. page program operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 12. random data input during sequential data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 13. multiplane page program waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 8 figure 14. copy back program (without readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 figure 15. copy back program (with readout of data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 16. page copy back program with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 17. multiplane copy back program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 18. block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 figure 19. multiplane block erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 20. page organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 figure 21. bad block management flowchart. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 22. garbage collection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 23. error detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 24. equivalent testing circuit for ac characteristics measurement . . . . . . . . . . . . . . . . . . . . . . 51 figure 25. command latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 figure 26. address latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 27. data input latch ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 28. sequential data output after read ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 29. sequential data output after read ac waveforms (edo mode) . . . . . . . . . . . . . . . . . . . . . 56 figure 30. read status register or read edc status register ac waveform. . . . . . . . . . . . . . . . . . . 57 figure 31. read status enhanced waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 32. read electronic signature ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 33. read onfi signature waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 figure 34. page read operation ac waveform. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 figure 35. page program ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 36. block erase ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 37. reset ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 figure 38. program/erase enable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 39. program/erase disable waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 40. read parameter page waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 41. ready/busy ac waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 42. ready/busy load circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 figure 43. resistor value versus waveform timings for ready/busy signal. . . . . . . . . . . . . . . . . . . . . 64 figure 44. data protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 45. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline . . . . . . . . . . . . 65 figure 46. lga52 12 x 17 mm, 1 mm pitch, package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
nand04g-b2d, nand08g -bxc description 7/69 1 description the nand04g-b2d and nand08g-bxc are part of the nand flash 2112 byte/1056 word page family of non-volatile flash memories. they use nand cell technology have a density of 4 gbits and 8 gbits, respectively. the nand04g-b2d memory array is split into 2 planes of 2048 blocks each. this multiplane architecture makes it possible to program 2 pages at a time (one in each plane), or to erase 2 blocks at a time (one in each plane). this feature reduces the average program and erase times by 50%. the nand08g-bxc is a stacked device that combines two nand04g-b2d dice, both of which feature a multip lane architecture. in the nand08g-b2c devices, only one of the memory components can be enabled at a time, therefore, operations can only be performed on one of the memory components at any one time. in the nand08g-b4c devices, each nand04g-b2d die can be accessed independently using two sets of signals. the devices operate from a 1.8 v or 3 v voltage supply. depending on whether the device has a x8 or x16 bus width, the page size is 2112 bytes (2048 + 64 spare) or or 1056 words (1024 + 32 spare), respectively. the address lines are multiplexed with the data input/output signals on a multiplexed x8 input/output bus. this interface reduces the pin count and makes it possible to migrate to other densities without changing the footprint. each block can be programmed and erased over 100 000 cycles with ecc (error correction code) on. to extend the lifetime of nand flash devices, the implementation of an ecc is strongly recommended. a write protect pin is available to provide hardware protection against program and erase operations. the devices feature an open-drain ready/busy output that identifies if the p/e/r (program/erase/read) controller is currently active. the use of an open-drain output allows the ready/busy pins from several memories to connect to a single pull-up resistor. a copy back program command is available to optimize the management of defective blocks. when a page program operation fails, the data can be programmed in another page without having to resend the data to be programmed. an embedded error detection code is automatically executed after each copy back operation: 1 error bit can be detected for every 528 bits. with this feature it is no longer ne cessary, nor recommended, to use an external 2- bit ecc to detect copy back operation errors. the devices have a cache read feature that improves the read throughput for large files. during cache reading, the device loads the data in a cache register wh ile the previous data is transferred to the i/o buffers to be read. the devices have the chip enable ?don?t care? feature, which allows code to be directly downloaded by a microcontroller. this is possible because chip enable transitions during the latency time do not stop the read operation. both the nand04g-b2d and nand08g-bxc support the onfi 1.0 specification.
description nand04g-b2d, nand08g-bxc 8/69 two further features are available as options: extra non-volatile protection. an individual serial number that acts as an unique identifier. more information is available, upon completion of an nda (non-disclosure agreement), and therefore, the details are not described in this datasheet. for more information on these two options, contact your nearest st sales office. the devices are available in the tsop48 (12 x 20 mm) and lga52 (12 x 17 mm) packages. to meet environmental requirements, st offers the nand04g-b2d and nand08g-bxc in ecopack ? packages. for information on how to order these options, refer to table 34: ordering information scheme . devices are shipped from the factory with block 0 always valid and the memory content bits, in valid blocks, erased to ?1?. table 2: product description lists the part numbers and other information for all the devices able in the family. table 2. product description part number density bus width page size block size memory array operating voltage timings package sequential access time (min) random access time (max) page program (typ) block erase (typ) nand04gr3b2d 4 gb x8 2048+64 bytes 128 k+ 4 k bytes 64 pages x 4096 blocks 1.7 to 1.95 v 45 ns 25 s 200 s 1.5ms lga52 nand04gw3b2d 2.7 to 3.6 v 25 ns tsop48 lga52 nand04gr4b2d x16 1024+ 32 words 64 k + 2 k words 1.7 to 1.95 v 45 ns (1) nand04gw4b2d 2.7 to 3.6 v 25 ns nand08gr3b2c 8 gb x8 2048+64 bytes 128 k + 4 k bytes 64 pages x 8192 blocks 1.7 to 1.95 v 45 ns 25 s 200 s 1.5ms lga52 (2) nand08gw3b2c 2.7 to 3.6 v 25 ns tsop48 lga52 (2) nand08gr4b2c x16 1024+ 32 words 64 k + 2 k words 1.7 to 1.95 v 45 ns (1)(2) nand08gw4b2c 2.7 to 3.6 v 25 ns nand08gr3b4c x8 2048+64 bytes 128 k + 4 k bytes 1.7 to 1.95 v 45 ns lga52 (2) nand08gw3b4c x8 2.7 to 3.6 v 25 ns 1. x16 organization is only available for mcp products. 2. the nand08g-bxc is composed of two 4-gbit dice.
nand04g-b2d, nand08g -bxc description 9/69 figure 1. logic block diagram 1. the nand08g-b4c devices have two separat e sets of signals for each 4 gb die. figure 2. logic diagram 1. the nand08g-b4c devices have two separat e sets of signals for each 4 gb die. address register/counter command interface logic p/e/r controller, high voltage generator wp i/o buffers & latches e w ai13166b r y decoder page buffer nand flash memory array x decoder i/o0-i/o7 (x8/x16) i/o8-i/o15 (x16) command register cl al cache register rb ai13167b w v dd nand flash e v ss wp al cl rb r i/o0-i/o7 (x8/x16) i/o8-i/o15 (x16)
description nand04g-b2d, nand08g-bxc 10/69 table 3. signal names (1) 1. the nand08g-b4c devices have two separat e sets of signals for each 4 gb die. signal function direction i/o0-7 data input/outputs, address inpu ts, or command inputs (x8/x16 devices) input/output i/o8-15 data input/outputs (x 16 devices) input/output al address latch enable input cl command latch enable input e chip enable input r read enable input rb ready/busy (open-drain output) output w write enable input wp write protect input v dd supply voltage power supply v ss ground ground nc not connected internally n/a du do not use n/a
nand04g-b2d, nand08g -bxc description 11/69 figure 3. tsop48 connections fo r nand04g-b2d and nand08g-bxc i/o3 i/o2 i/o6 r rb nc i/o4 i/o7 ai13168b nand flash 12 1 13 24 25 36 37 48 e i/o1 nc nc nc nc nc nc nc wp w nc nc nc v ss v dd al nc nc cl nc i/o5 nc nc nc i/o0 nc nc nc nc nc v dd nc nc nc v ss nc nc nc nc
description nand04g-b2d, nand08g-bxc 12/69 figure 4. lga52 connections for nand04g-b2d and nand08g-b2c devices ai13634b nc od oc ob al oa 8 7 6 5 4 3 2 1 nc of oe nc nc nc nc nc 0 nc nc nc nc nc nc nc nc nc nc a b c d e f g h j k l m n v ss nc i/o1 i/o3 v ss wp cl i/o0 nc i/o2 w i/o4 v ss i/o6 e nc rb v dd v ss i/o7 i/o5 v dd nc nc nc nc r nc nc nc nc nc nc nc nc
nand04g-b2d, nand08g -bxc description 13/69 figure 5. lga52 connections for the nand08g-b4c devices 1. the nand08g-b4c devices have two separat e sets of signals for each 4 gb die. nc od oc ob al 1 oa 8 7 6 5 4 3 2 1 i/o0 2 of oe nc i/o1 2 i/o2 2 nc nc 0 nc nc nc nc nc nc nc nc nc nc a b c d e f g h j k l m n w 2 v ss al 2 i/o1 1 i/o3 1 v ss wp 1 cl 1 cl 2 i/o0 1 i/o3 2 i/o2 1 w 1 i/o4 1 v ss i/o6 1 e 1 e 2 rb 1 wp 2 v dd v ss i/o7 1 i/o5 1 v dd r 2 nc i/o7 2 nc i/o6 2 i/o5 2 rb 2 r 1 i/o4 2
memory array organizati on nand04g-b2d, nand08g-bxc 14/69 2 memory array organization the memory array of the devices is made up of nand structures where 32 cells are connected in series. it is organized into blocks where each block contains 64 pages. the array is split into two areas, the main area, and the spare area. the main area of the array is used to store data, and the spare area typically stores error correction codes, software flags, or bad block identification. in x8 devices, the pages are split into a 2048-byte main area and a spare area of 64 bytes. in x16 devices, the pages are split into a 1024-word main area and a spare area of 32 words. refer to figure 6: memory array organization . bad blocks in the x8 devices, the nand flash 2112 byte/1056 word page devices may contain bad blocks, which are blocks that contain one or more invalid bits whose reliability is not guaranteed. additional bad blocks may develop during the lifetime of the device. the bad block information is written prior to shipping (refer to section 9.1: bad block management for more details). ta bl e 4 shows the minimum number of valid blocks. the values shown include both the bad blocks that are present when the device is shipped and the bad blocks that could develop later on. block 0 is guaranteed to be valid up to 1000 write/erase cycles with 1 bit ecc. these blocks need to be managed using bad blocks management, block replacement, or error correction codes (refer to section 9: software algorithms ). table 4. valid blocks density of device min max 4 gbits 4016 4096 8 gbits (1) 1. the nand08g-bxc devices are comp osed of two 4-gbit dice. the mini mum number of valid blocks is 4016 for each die. 8032 8192
nand04g-b2d, nand08g-bxc me mory array organization 15/69 figure 6. memory array organization ai13170b x8 bus width plane = 2048 blocks, block = 64 pages, page = 2112 bytes (2048 + 64) 2048 bytes 2048 bytes 64 bytes block 64 bytes page page buffer, 2112 bytes main area 2,048 bytes 2048 bytes spare area 64 bytes 8 bits 64 bytes 8 bits page buffer, 2112 bytes main area spare area 2-page buffer, 2 x 2112 bytes first plane second plane x16 bus width plane = 2048 blocks, block = 64 pages, page = 1056 words (1024 + 32) 1024 words 1024 words 32 words block 32 words page page buffer, 1056 bytes main area 1024 words 1024 words spare area 32 words 16 bits 32 words 16 bits page buffer, 1056 bytes main area spare area 2-page buffer, 2 x 1056 bytes first plane second plane
signal descriptions nand04 g-b2d, nand08g-bxc 16/69 3 signal descriptions see figure 2: logic diagram and table 3: signal names for a brief overview of the signals connected to this device. the nand08g-b4c devi ces have two separate sets of signals for each 4 gb die. 3.1 inputs/outputs (i/o0-i/o7) input/outputs 0 to 7 input the selected address, output the data during a read operation, or input a command or data during a write operation. the inputs are latched on the rising edge of write enable. i/o0-i/o7 are left floating when the device is deselected or the outputs are disabled. 3.2 inputs/outputs (i/o8-i/o15) input/outputs 8 to 15 are only available in x16 devices. they output the data during a read operation or input data during a write operation. command and address inputs only require i/o0 to i/o7. the inputs are latched on the rising edge of write enable. i/o8-i/o15 are left floating when the device is deselected or the outputs are disabled. 3.3 address latch enable (al) the address latch enable activates the latching of the address inputs in the command interface. when al is high, the inputs are latched on the rising edge of write enable. 3.4 command latch enable (cl) the command latch enable activates the latching of the command inputs in the command interface. when cl is high, the inputs are latched on the rising edge of write enable. 3.5 chip enable (e ) the chip enable input, e , activates the memory control logic, input buffers, decoders and sense amplifiers. when chip enable is low, v il , the device is selected. if chip enable goes high, v ih , while the device is busy, the device remains selected and does not go into standby mode. 3.6 read enable (r ) the read enable pin, r , controls the sequential data output during read operations. data is valid t rlqv after the fallin g edge of r . the falling edge of r also increments the internal column address co unter by one.
nand04g-b2d, nand08g-bxc signal descriptions 17/69 3.7 write enable (w ) the write enable input, w , controls writing to the command interface, input address and data latches. both addresses and data are latched on the rising edge of write enable. during power-up and power-down a recovery time of 10 s (min) is required before the command interface is ready to accept a command. it is recommended to keep write enable high during the recovery time. 3.8 write protect (wp ) the write protect pin is an input that gives a hardware protection against unwanted program or erase operations. when write protect is low, v il , the device does not accept any program or erase operations. it is recommended to keep the write protect pin low, v il , during power-up and power-down. 3.9 ready/busy (rb ) the ready/busy output, rb , is an open-drain output that id entifies if the p/e/r controller is currently active. when ready/busy is low, v ol , a read, program or erase operation is in progress. when the operation completes, ready/busy goes high, v oh . the use of an open-drain output allows the ready/busy pins from several memories to be connected to a single pull-up resistor. a low then indicates that one or more of the memories is busy. during power-up and power-down a minimum recovery time of 10 s is required before the command interface is ready to accept a command. during this period the rb signal is low, v ol . refer to section 12.1: ready/busy signal electrical characteristics for details on how to calculate the value of the pull-up resistor. 3.10 v dd supply voltage v dd provides the power supply to the internal core of the memory device. it is the main power supply for all operations (read, program and erase). an internal voltage detector disables all functions whenever v dd is below v lko (see ta bl e 2 9 ) to protect the device from any involuntary program/erase during power-transitions. each device in a system should have v dd decoupled with a 0.1 f capacitor. the pcb track widths should be sufficient to carry the required program and erase currents. 3.11 v ss ground ground, v ss, is the reference for the power supply. it must be connected to the system ground.
bus operations nand04g-b2d, nand08g-bxc 18/69 4 bus operations there are six standard bus operations that control the memory, as described in this section. see table 5: bus operations for a summary of these operations. typically, glitches of less than 5 ns on ch ip enable, write enable, and read enable are ignored by the memory and do not affect bus operations. 4.1 command input command input bus operations give commands to the memory. commands are accepted when chip enable is low, command latch enable is high, address latch enable is low, and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input commands. see figure 25 and ta b l e 3 0 for details of the timings requirements. 4.2 address input address input bus operations input the memory addresses. five bus cycles are required to input the addresses (refer to table 6: address insertion (x8 devices) and table 7: address insertion (x16 devices) ). the addresses are accepted when chip enable is low, address latch enable is high, command latch enable is low, and read enable is high. they are latched on the rising edge of the write enable signal. only i/o0 to i/o7 are used to input addresses. see figure 26 and ta b l e 3 0 for details of the timings requirements. 4.3 data input data input bus operations input the data to be programmed. data is accepted only when chip enable is low, address latch enable is low, command latch enable is low, and read enable is high. the data is latched on the rising edge of the write enable signal. the data is input sequentially using the write enable signal. see figure 27 and ta b l e 3 0 and ta b l e 3 1 for details of the timings requirements. 4.4 data output data output bus operations read the data in the memory array, the status register, the electronic signature, and the unique identifier. data is output when chip enable is low, writ e enable is high, address latch enable is low, and command latch enable is low. the data is output sequentially using the read enable signal.
nand04g-b2d, nand08g -bxc bus operations 19/69 if the read enable pulse frequency is lower then 33 mhz (t rlrl higher than 30 ns), the output data is latched on the rising edge of read enable signal (see figure 28 ). for higher frequencies (t rlrl lower than 30 ns), the edo (extended data out) mode must be used. in this mode, data output bus operations are valid on the input/output bus for a time of t rlqx after the falling edge of read enable signal (see figure 29 ). see ta bl e 3 1 for details on the timings requirements. 4.5 write protect write protect bus operations protect the memory against program or erase operations. when the write protect signal is low the device does not accept program or erase operations, and, therefore, the contents of the memory array cannot be altered. the write protect signal is not latched by write enable to ensure protection, even during power-up. 4.6 standby when chip enable is high the memory enters standby mode, the device is deselected, outputs are disabled, and power consumption is reduced. table 5. bus operations bus operation e al cl r w wp i/o0 - i/o7 i/o8 - i/o15 (1) 1. only for x16 devices. command input v il v il v ih v ih rising x (2) 2. wp must be v ih when issuing a program or erase command. command x address input v il v ih v il v ih rising x address x data input v il v il v il v ih rising v ih data input data input data output v il v il v il falling v ih x data output data output write protect x x x x x v il xx standby v ih xx x xv il /v dd xx table 6. address insertion (x8 devices) bus cycle (1) 1. any additional address i nput cycles are ignored. i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd v il v il v il v il a11 a10 a9 a8 3 rd a19 a18 a17 a16 a15 a14 a13 a12 4 th a27 a26 a25 a24 a23 a22 a21 a20 5 th v il v il v il v il v il a30 (2) 2. a30 is only valid for the nand08g-bxc devices. a29 a28
bus operations nand04g-b2d, nand08g-bxc 20/69 table 7. address insertion (x16 devices) bus cycle (1) 1. any additional address i nput cycles are ignored. i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 1 st a7 a6 a5 a4 a3 a2 a1 a0 2 nd v il v il v il v il v il a10 a9 a8 3 rd a18 a17 a16 a15 a14 a13 a12 a11 4 th a26 a25 a24 a23 a22 a21 a20 a19 5 th v il v il v il v il v il a29 (2) 2. a29 is only valid for the nand08g-bxc devices. a28 a27 table 8. address definition (x8 devices) address definition a0 - a11 column address a12 - a17 page address a18 - a29 block address(nand04g-b2d) a18 - a30 block address (nand08g-bxc) a18 = 0 first plane a18 = 1 second plane table 9. address definition (x16 devices) address definition a0 - a10 column address a11 - a16 page address a17 - a28 block address (nand04g-b2d) a17 - a29 block address (nand08g-bxc) a18 = 0 first plane a18 = 1 second plane
nand04g-b2d, nand08g -bxc command set 21/69 5 command set all bus write operations to the device are interpreted by the command interface. the commands are input on i/o0-i/o7 and are latched on the rising edge of write enable when the command latch enable signal is high. device operations are selected by writing specific commands to the command register. the two-step command sequences for program and erase operations are imposed to maximize data security. ta bl e 1 0 summarizes the commands. table 10. commands command (1) 1. commands in bold are referring to onfi 1.0 specifications. bus write oper ations commands accepted during busy 1 st cycle 2 nd cycle 3 rd cycle 4 th cycle read 00h 30h ? ? random data output 05h e0h ? ? cache read (sequential) 31h ? ? ? enhanced cache read (random) 00h 31h ? ? exit cache read 3fh ? ? ? yes (2) 2. only during cache read busy. page program (sequential input default) 80h 10h ? ? random data input 85h ? ? ? multiplane page program (3) 80h 11h 81h 10h multiplane page program 80h 11h 80h 10h copy back read 00h 35h ? ? copy back program 85h 10h ? ? multiplane copy back program (3) 3. command maintained for backward compatibility. 85h 11h 81h 10h multiplane copy back program 85h 11h 85h 10h block erase 60h d0h ? ? multiplane block erase (3) 60h 60h d0h ? multiplane block erase 60h d1h 60h d0h reset ffh ? ? ? ye s read electronic signature 90h ? ? ? read status register 70h ? ? ? ye s read status enhanced 78h ? ? ? yes read parameter page ech ? ? ? read edc status register 7bh ? ? ?
device operations nand 04g-b2d, nand08g-bxc 22/69 6 device operations this section provides details of the device operations. 6.1 read memory array at power-up the device defaults to read mode. to enter read mode from another mode, the read command must be issued (see table 10: commands ). 6.1.1 random read each time the read command is issued, the first read is random read. 6.1.2 page read after the first random read access, the page data (2112 bytes or 1056 words) are transferred to the page buffer in a time of t whbh (see ta bl e 3 1 ). once the transfer is complete, the ready/busy signal goes high. the data can then be read sequentially (from selected column address to last column address) by pulsing the read enable signal. the device can output random data in a page, instead of consecutive sequential data, by issuing a random data output command. the random data output command can be used to skip some data during a sequential data output. the sequential operation can be resumed by changing the column address of the next data to be output, to the address which follows the random data output command. the random data output command can be issued as many times as required within a page. the random data output command is not accepted during cache read operations.
nand04g-b2d, nand08g-bxc device operations 23/69 figure 7. read operations cl e w al r i/o rb 00h ai12469 busy command code data output (sequentially) address input tblbh1 30h command code
device operations nand 04g-b2d, nand08g-bxc 24/69 figure 8. random data output during sequential data output 6.2 cache read the cache read operation improves the read throughput by reading data using the cache register. as soon as the user starts to read one page, the device automatically loads the next page into the cache register. a read page command, as defined in section 6.1.1: random read , is issued prior to the first read cache command in a read cache sequence. once the data output of the page read command terminates, the cache read command can be issued as follows: 1. issue a sequential cache read command to copy the next page in sequential order to the cache register. 2. issue a random cache read command to copy the page addressed in this command to the cache register. the two commands can be used interchangeably, in any order. when there are no more pages are to be read, the final page is copied into the cache register by issuing the exit cache read command. a read cache command must not be issued after the last page of the device is read. see figure 9: cache read (sequential) operation and figure 10: cache read (random) operation for examples of the two sequences. i/o rb address inputs ai08658b data output busy tblbh1 (read busy time) 00h cmd code 30h address inputs data output 05h e0h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code cmd code cmd code 2 add cycles main area spare area col add 1,2 r w trhwl
nand04g-b2d, nand08g-bxc device operations 25/69 after the sequential cache read or random cache read command has been issued, the ready/busy signal goes low and the status register bits are set to sr5 =' 0' and sr6 ='0' for a period of cache read busy time, t rcbsy , while the device copies the next page into the cache register. after the cache read busy time has passed, the ready/busy signal goes high and the status register bits are set to sr5 = '0' and sr 6 = '1', signifying that the cache register is ready to download new data. data of the previously read page can be output from the page buffer by toggling the read enable signal. data output always begins at column address 00h, but the random data output command is also supported. figure 9. cache read (sequential) operation figure 10. cache read (random) operation i/o0-7 rb address inputs ai13176b 00h 30h tblbh1 (read busy time) r trcbsy trcbsy 31h 3fh data outputs data outputs (read cache busy time) (read cache busy time) read setup code read code repeat as many times as ncessary. cache read sequential code exit cache read code busy i/o0-7 rb address inputs ai13176c 00h 30h tblbh1 (read busy time) r trcbsy trcbsy 00h data outputs (read cache busy time) (read cache busy time) read setup code read code repeat as many times as ncessary. read setup code exit cache read code busy 31h enhanced cache read (random) code 3fh data outputs address inputs
device operations nand 04g-b2d, nand08g-bxc 26/69 6.3 page program the page program operation is the standard operation to program data to the memory array. generally, the page is programmed sequentially, however, the device does support random input within a page. it is recommended to address pages sequentially within a given block. the memory array is programmed by page, however, partial page programming is allowed where any number of bytes (1 to 2112) or words (1 to 1056) can be programmed. the maximum number of consecutive, partial-page program operations allowed in the same page is four. after exceeding four operations a block erase command must be issued before any further program operations can take place in that page. 6.3.1 sequential input to input data sequentially the addresses must be sequential and remain in one block. for sequential input each page program operation consists of the following five steps : 1. one bus cycle is required to set up the page program (sequential input) command (see table 10: commands ). 2. five bus cycles are then required to input the program address (refer to ta bl e 6 : address insertion (x8 devices) and table 7: address insertion (x16 devices) ). 3. the data is then loaded into the data registers. 4. one bus cycle is required to issue the page program confirm command to start the p/e/r controller. the p/e/r only starts if the data has been loaded in step 3. 5. the p/e/r controller then programs the data into the array. see figure 11: page program operation for more information. 6.3.2 random data input in page during a sequential input operation, the next sequential address to be programmed can be replaced by a random address by issuing a random data input command. the following two steps are required to issue the command: 1. one bus cycle is required to set up the random data input command (see ta bl e 1 0 : commands ). 2. two bus cycles are then required to input the new column address (refer to ta bl e 6 : address insertion (x8 devices) ). random data input can be repeated as often as required in any given page. once the program operation has started, the status register can be read using the read status register command. during program operations the status register only flags errors for bits set to '1' that have not been successfully programmed to '0'. during the program operation, only the read status register and reset commands are accepted; all other commands are ignored. once the program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. the device remains in read status register mode until another valid command is written to the command interface.
nand04g-b2d, nand08g-bxc device operations 27/69 figure 11. page program operation figure 12. random data input during sequential data input i/o rb address inputs sr0 ai08659 data input 10h 70h 80h page program setup code confirm code read status register busy tblbh2 (program busy time) i/o address inputs ai08664 data intput 80h cmd code address inputs data input 85h 5 add cycles main area spare area col add 1,2 row add 1,2,3 cmd code 2 add cycles main area spare area col add 1,2 rb busy tblbh2 (program busy time) sr0 10h 70h confirm code read status register
device operations nand 04g-b2d, nand08g-bxc 28/69 6.4 multiplane page program the devices support multiplane page program, which enables the programming of two pages in parallel, one in each plane. a multiplane page program operation requires the following two steps: 1. the first step serially loads up to two pages of data (4224 bytes) into the data buffer. it requires: ? one clock cycle to set up the page program command (see section 6.3.1: sequential input ). ? 5 bus write cycles to input the first page address and data. the address of the first page must be within the first plane (a18 = 0). ? one bus write cycle to issue the page program confirm code. after this, the device is busy for a time of t ipbsy. ? when the device returns to the ready state (ready/busy high), a multiplane page program setup code must be issued, followed by the 2nd page address (5 write cycles) and data. the address of the 2nd page must be within the second plane (a18 = 1). 2. the 2nd step programs in parallel the two pages of data loaded into the data buffer into the appropriate memory pages. it is started by issuing a the program confirm command. as for standard page program operation, the device supports random data input during both data loading phases. once the multiplane page program operation has started, that is during a delay of t ipbsy , the status register can be read using the read status register command. once the multiplane page program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the multiplane page program fails, an error is signaled on bit sr0 of the status register. to know which page of the two planes failed, the read status enhanced command must be issued twice, once for each plane (see section 6.12 ) . figure 13 provides a description of multiplane page program waveforms. figure 13. multiplane page program waveform 1. the 81h setup code is also acc epted for backward compatibility. i/o rb address inputs ai13171b data input 11h 80h (1) 80h page program setup code confirm code multiplane page program setup code busy tipbsy a18=0 address inputs sr0 data input 10h 70h confirm code read status register a18=1 busy tblbh2 (program busy time)
nand04g-b2d, nand08g-bxc device operations 29/69 6.5 copy back program the copy back program operation copies the data stored in one page and reprograms it in another page. the copy back program operation does not require external memory and so the operation is faster and more efficient because the reading and loading cycles are not required. the operation is particularly useful when a portion of a block is updated and the rest of the block needs to be copied to the newly assigned block. the nand04g-b2d and nand08g-bxc devices feature automatic edc during a copy back operation. consequently, external ecc is no longer required. the errors detected during copy back operations can be read by performing a read edc status register operation (see section 6.13: read edc status register ). see also section 6.9 for details of edc operations. the copy back program operation requires the following four steps: 1. the first step reads the source page. the operation copies all 2112 bytes from the page into the data buffer. it requires: ? one bus write cycle to set up the command ? 5 bus write cycles to input the source page address ? one bus write cycle to issu e the confirm command code 2. when the device returns to the ready state (ready/busy high), optional data readout is allowed by pulsing r ; the next bus write cycle of the command is given with the 5 bus cycles to input the target page address. see ta bl e 1 1 for the addresses that must be the same for the source and target page. 3. issue the confirm command to start the p/e/r controller. to see the data input cycle for modifying the source page and an example of the copy back program operation, refer to figure 14: copy back program (without readout of data) . figure 16: page copy back program with random data input shows a data input cycle to modify a portion or a multiple distant portion of the source page. figure 14. copy back program (without readout of data) 1. copy back program is only permitted bet ween odd address pages or even address pages. table 11. copy back program addresses density source and target page addresses 4 gbits same a18 8 gbits same a18 and a30 i/o rb source add inputs ai09858b 85h copy back code read code read status register target add inputs tblbh1 (read busy time) busy tblbh2 (program busy time) 00h 10h 70h sr0 busy 35h
device operations nand 04g-b2d, nand08g-bxc 30/69 figure 15. copy back program (with readout of data) figure 16. page copy back program with random data input 6.6 multiplane copy back program in addition to multiplane page program, the nand04g-b2d and nand08g-bxc devices support multiplane copy back program. a multiplane copy back program command requir es exactly the same steps as a multiplane page program command, and must satisfy the same time constraints (see section 6.4: multiplane page program ). prior to executing the multiplane copy back program operation, two single-page read operations must be executed to copy back the first page from the first plane and the second page from the second plane. the edc check is also performed during the multiplane copy back program. errors during multiplane copy back operations can be detected by performing a read edc status register operation (see section 6.13: read edc status register ). if the multiplane copy back program fails, an error is signaled on bit sr0 of the status register. to know which page of the two planes failed, the read status enhanced command must be executed twice, once for each plane (see section 6.12 ). i/o rb source add inputs ai09858c 85h copy back code read code read status register target add inputs tblbh1 (read busy time) busy tblbh2 (program busy time) 00h 10h 70h sr0 busy 35h data outputs i/o rb source add inputs ai11001 85h read code target add inputs tblbh1 (read busy time) 00h busy 35h 85h data 2 cycle add inputs data copy back code 10h 70h unlimited number of repetitions busy tblbh2 (program busy time) sr0
nand04g-b2d, nand08g-bxc device operations 31/69 figure 17 provides a description of multiplane copy back program waveform. figure 17. multiplane copy back program 1. the 81h setup code is also acc epted for backward compatibility. 6.7 block erase erase operations are done one block at a time. an erase operation sets all of the bits in the addressed block to ?1?. all previous data in the block is lost. an erase operation consists of the following three steps (refer to figure 18: block erase ): 1. one bus cycle is required to set up the block erase command. only addresses a18- a29 are used; all other address inputs are ignored. 2. three bus cycles are then required to load the address of the block to be erased. refer to table 8: address definition (x8 devices) for the block addresses of each device. 3. one bus cycle is required to issue the block erase confirm command to start the p/e/r controller. the operation is initiated on the rising edge of write enable, w , after the confirm command is issued. the p/e/r controller handles block erase and implements the verify process. during the block erase operation, only the read status register and reset commands are accepted; all other commands are ignored. once the program operation has completed, the p/e/r controller bit sr6 is set to ?1? and the ready/busy signal goes high. if the operation completed successfully, the write status bit sr0 is ?0?, otherwise it is set to ?1?. figure 18. block erase i/o rb source add inputs ai13172b 00h read code read code source add inputs tblbh1 (read busy time) busy tblbh1 (read busy time) 00h busy 35h read status register 10h 70h sr0 a18=0 35h a18 = 1 85h copy back code target add inputs a18 = 0 11h copy back code target add inputs a18 = 1 tipbsy busy tblbh2 (program busy time) busy 85h (1) i/o rb block address inputs sr0 ai07593 d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time)
device operations nand 04g-b2d, nand08g-bxc 32/69 6.8 multiplane block erase the multiplane block erase operation allows the erasure of two blocks in parallel, one in each plane. this operation consists of the following three steps (refer to figure 19: multiplane block erase ): 1. 8 bus cycles are required to set up the bl ock erase command and load the addresses of the blocks to be erased. the setup command followed by the address of the block to be erased must be issued for each block. t iebsy busy time is required between the insertion of first and the second block addresses. as for multiplane page program operations, the address of the first and second page must be within the first plane (a18 = 0) and second plane (a8 = 1), respectively. 2. one bus cycle is then required to issue the multiplane block erase confirm command and start the p/e/r controller. if the multiplane block erase fails, an error is signaled on bit sr0 of the status register. to know which page of the two planes failed, the read status enhanced command must be issued twice, once for each plane (see section 6.12 ). figure 19. multiplane block erase 1. the d1h confirm code is required by the onfi 1.0 command set. to maintain backward compatibility, the d1h confirm code can optionally be ignored, and then the tiebsy busy time does not occur. 6.9 error detection code (edc) the edc (error detection code) is performed automatically during all program operations. it starts immediately after the device becomes busy. the edc detects 1 single bit error per edc unit. each edc unit has a density of 528 bytes (or 264 words), split into 512 bytes of main area and 16 bytes of spare area (or 256 + 8 words). refer to ta bl e 1 2 and figure 20 for edc unit addresses definition. to properly use the edc, the following conditions apply: page program operations must be performed on a whole page, or on whole edc unit(s). the modification of the content of an edc unit using a random data input before the copy back program, must be performed on the whole edc unit. it can only be done once per edc unit. any partial modification of the edc unit results in the corruption of the on-chip edcs. i/o block address inputs sr0 ai13173b d0h 70h 60h block erase setup code confirm code read status register busy tblbh3 (erase busy time) a18 = 0 block address inputs d1h (1) multiplane block erase code a18 = 1 rb tiebsy 60h block erase setup code
nand04g-b2d, nand08g-bxc device operations 33/69 edc results can be retrieved only during copy back program and multiplane copy back using the read edc status register command (see section 6.13 ). figure 20. page organization table 13. address definition for edc units (x16 devices) 6.10 reset the reset command is used to reset the command interface and status register. if the reset command is issued during any operation, the operation is aborted. if the aborted operation is a program or erase, the contents of the memory locations being modified are no longer valid as the data is partially programmed or erased. if the device has already been reset, then the new reset command is not accepted. the ready/busy signal goes low for t blbh4 after the reset command is issued. the value of t blbh4 depends on the operation that the device was performing when the command was issued. refer to ta b l e 3 1 for the values. ai13179b a area (512 bytes/ 256 words) main area (2048 bytes/1024 words) spare area (64 bytes/32 words) page = 4 edc units b area (512 bytes/ 256 words) c area (512 bytes/ 256 words) d area (512 bytes/ 256 words) e area (16 bytes/ 8 words) f area (16 bytes/ 8 words) g area (16 bytes/ 8 words) h area (16 bytes/ 8 words) table 12. address definition for edc units (x8 devices) edc unit main area spare area area name column address area name column address 1st 528-byte edc unit a 0 to 511 e 2048 to 2063 2nd 528-byte edc unit b 512 to 1023 f 2064 to 2079 3rd 528-byte edc unit c 1024 to1535 g 2080 to 2095 4th 528-byte edc unit d 1536 to 2047 h 2096 to 2111 edc unit main area spare area area name column address area name column address 1st 264-word edc unit a 0 to 255 e 1024 to 1031 2nd 264-word edc unit b 256 to 511 f 1032 to 1039 3rd 264-word edc unit c 512 to 767 g 1040 to 1047 4th 264-word edc unit d 768 to 1023 h 1048 to 1055
device operations nand 04g-b2d, nand08g-bxc 34/69 6.11 read status register the devices contain a status register that provides information on the current or previous program or erase operation. the various bits in the status register convey information and errors on the operation. the status register is read by issuing the read status register command. the status register information is present on the output data bus (i/o0-i/ o7) on the falling edge of chip enable or read enable, whichever occurs last. when several memories are connected in a system, the use of chip enable and read enab le signals allows the system to poll each device separately, even when the ready/busy pins are common-wired. it is not necessary to toggle the chip enable or read enable signals to update the contents of the status register. after the read status register command has been issued, the device remains in read status register mode until another command is is sued. therefore, if a read status register command is issued during a random read cycle, a new read command must be issued to continue with a page read operation. the status register bits are summarized in table 14: status register bits . refer to ta b l e 1 4 in conjunction with the following sections. 6.11.1 write protection bit (sr7) the write protection bit identifies if the device is protected or not. if the write protection bit is set to ?1?, the device is not protected and program or erase operations are allowed. if the write protection bit is set to ?0? the device is protected and program or erase operations are not allowed. 6.11.2 p/e/r controller and cache ready/busy bit (sr6) status register bit sr6 has two different functions depending on the current operation. during cache operations, sr6 acts as a cache ready/busy bit, which indicates whether the cache register is ready to accept new data. when sr6 is set to '0', the cache register is busy, and when sr6 is set to '1', the cache register is ready to accept new data. during all other operations, sr6 acts as a p/e/r controller bit, which indicates whether the p/e/r controller is active or inactive. when th e p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is bu sy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). 6.11.3 p/e/r contro ller bit (sr5) the program/erase/read controller bit indicates whether the p/e/r controller is active or inactive during cache operations. when the p/e/r controller bit is set to ?0?, the p/e/r controller is active (device is bu sy); when the bit is set to ?1?, the p/e/r controller is inactive (device is ready). note: this bit is only valid for cache operations. 6.11.4 error bit (sr0) the error bit identifies if any errors have been detected by the p/e/r controller. the error bit is set to ?1? when a program or erase operation has failed to write the correct data to the memory. if the error bit is set to ?0? the operation has completed successfully.
nand04g-b2d, nand08g-bxc device operations 35/69 6.11.5 sr4, sr3, sr2 and sr1 are reserved 6.12 read status enhanced in nand flash devices with multiplane architectu re, it is possible to independently read the status register of a single plane using the read status enhanced command. if the error bit of the status register, sr0, reports an error during or after a multiplane operation, the read status enhanced command is used to know which of the two planes contains the page that failed the operation. three address cycles are required to address the selected block and page (a18-0). the output of the read status enhanced command has the same coding as the read status command. see ta b l e 1 4 for a full description and figure 31 for the read status enhanced waveform. 6.13 read edc status register the devices contain an edc status register, whic h provides information on the errors that occurred during the read cycles of the copy back and multiplane copy back operations. in the case of multiplane copy back program, it is not possible to distinguish which of the two read operations caused the error. the edcs status register is read by issuing the read edc status register command. after issuing the read edc status register command, a read cycle outputs the content of the edc status register to the i/o pins on the falling edge of chip enable or read enable signals, whichever occurs last. the operation is similar to read status register command. table 15: edc status register bits summarizes the edc status register bits. see figure 30 for a description of read edc status register waveforms. table 14. status register bits bit name logic level definition sr7 write protection '1' not protected '0' protected sr6 program/erase/read controller '1' p/e/r controller inactive, device ready '0' p/e/r controller active, device busy sr5 program/erase/read controller (1) '1' p/e/r controller inactive, device ready '0' p/e/r controller active, device busy sr4, sr3, sr2, sr1 reserved ?don?t care? sr0 generic error ?1? error ? operation failed ?0? no error ? operation successful 1. only valid for cache operations.
device operations nand 04g-b2d, nand08g-bxc 36/69 6.14 read electronic signature the devices contain a manufacturer code and device code. the following three steps are required to read these codes: 1. one bus write cycle to issue the read electronic signature command (90h) 2. one bus write cycle to input the address (00h) 3. five bus read cycles to sequentially output the data (as shown in table 16: electronic signature ). table 15. edc status register bits bit name logic level definition 0 pass/fail ?1? copy back or multiplane copy back operation failed ?0? copy back or multiplane copy back operation succeeded 1 edc status ?1? error ?0? no error 2 edc validity ?1? valid ?0? invalid 3 reserved ?don?t care? - 4 reserved ?don?t care? - 5 ready/busy (1) 1. see table 14: status register bits for a description of sr5 and sr6 bits. ?1? ready ?0? busy 6 ready/busy (1) ?1? ready ?0? busy 7 write protect ?1? not protected ?0? protected
nand04g-b2d, nand08g-bxc device operations 37/69 table 16. electronic signature root part number byte 1 byte 2 byte 3 (see ta bl e 1 7 ) byte 4 (see ta b l e 1 8 ) byte 5 (see ta b l e 1 9 ) nand04gr3b2d nand08gr3b4c (1) 20h ach 10h 15h 54h nand04gw3b2d nand08gw3b4c (1) 20h dch 10h 95h 54h nand04gr4b2d 0020h bch 10h 55h 54h nand04gw4b2d 0020h cch 10h d5h 54h nand08gr3b2c 20h a3h 51h 15h 58h nand08gw3b2c 20h d3h 51h 95h 58h nand08gr4b2c 0020h b3h 51h 55h 58h nand08gw4b2c 0020h c3h 51h d5h 58h 1. for nand08g-b4c devices, each 4 gb di e returns its own electronic signature. table 17. electronic signature byte 3 i/o definition value description i/o1-i/o0 internal chip number 0 0 0 1 1 0 1 1 1 2 4 8 i/o3-i/o2 cell type 0 0 0 1 1 0 1 1 2-level cell 4-level cell 8-level cell 16-level cell i/o5-i/o4 number of simultaneously programmed pages 0 0 0 1 1 0 1 1 1 2 4 8 i/o6 interleaved programming between multiple devices 0 1 not supported supported i/o7 cache program 0 1 not supported supported
device operations nand 04g-b2d, nand08g-bxc 38/69 table 18. electronic signature byte 4 i/o definition value description i/o1-i/o0 page size (without spare area) 0 0 0 1 1 0 1 1 1 kbytes 2 kbytes 4 kbytes 8 kbytes i/o2 spare area size (byte/512 byte) 0 1 8 16 i/o7, i/o3 minimum sequential access time 0 0 1 0 0 1 1 1 30/50 ns 25 ns reserved reserved i/o5-i/o4 block size (without spare area) 0 0 0 1 1 0 1 1 64 kbytes 128 kbytes 256 kbytes 512 kbytes i/o6 organization 0 1 x8 x16 table 19. electronic signature byte 5 i/o definition value description i/o1 - i/o0 reserved 0 0 i/o3 - i/o2 plane number 0 0 0 1 1 0 1 1 1 plane 2 planes 4 planes 8 planes i/o6 - i/o4 plane size (without spare area) 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 64 mbits 128 mbits 256 mbits 512 mbits 1 gb 2 gb 4 gb 8 gb i/o7 reserved 0
nand04g-b2d, nand08g-bxc device operations 39/69 6.15 read onfi signature to recognize nand flash devices that are compatible with the onfi 1.0 command set, the read electronic signature can be issued, followed by an address of 20h. the next four bytes output is the onfi signature, which is the ascii encoding of the ?onfi? word. reading beyond four bytes produces indeterminate values. figure 33 provides a description of the read onfi signature waveform and ta bl e 2 0 provides the definition of the output bytes. 6.16 read parameter page the read parameter page command retrieves the data structure that describes the nand flash organization, features, timings and other behavioral parameters. this data structure enables the host processor to automatically recognize the nand flash configuration of a device. the whole data structure is repeated at least five times. see figure 40 for a description of the read parameter page waveform. the random data read command can be issued during execution of the read parameter page to read specific portions of the parameter page. the read status command may be used to check the status of read parameter page during execution. after completion of the read status command, 00h is issued by the host on the command line to continue with the data output flow for the read parameter page command. read status enhanced is not be used during execution of the read parameter page command. ta bl e 2 1 defines the parameter page data structure; for parameters that span multiple bytes, the least significant byte of the parameter corresponds to the first byte. values are reported in the parameter page in bytes when referring to items related to the size of data access (as in an x8 data acce ss device). for example, the chip returns how many data bytes are in a page. for a device that supports x16 data access, the host is required to convert byte values to word values for its use. unused fields are set to 0h. for more detailed information about parameter page data bits, refer to onfi specification 1.0, section 5.4.1. table 20. read onfi signature byte value ascii character 1st byte 4fh o 2nd byte 4eh n 3rd byte 46h f 4th byte 49h i 5th byte undefined undefined
device operations nand 04g-b2d, nand08g-bxc 40/69 table 21. parameter page data structure byte o/m (1) description revision information and features block 0-3 m parameter page signature ? byte 0: 4fh, "o" ? byte 1: 4eh, "n" ? byte 2: 46h, "f" ? byte 3: 49h, "i" 4-5 m revision number bit 2 to bit 15 reserved (0) bit 1 1 = supports onfi version 1.0 bit 0 reserved (0) 6-7 m features supported bit 5 to bit 15 reserved (0) bit 4 1 = supports odd to even page copyback bit 3 1 = supports interleaved operations bit 2 1 = supports non-sequential page programming bit 1 1 = supports multiple lun operations bit 0 1 = supports 16-bit data bus width 8-9 m optional commands supported bit 6 to bit 15 reserved (0) bit 5 1 = supports read unique id bit 4 1 = supports copyback bit 3 1 = supports read status enhanced bit 2 1 = supports get features and set features bit 1 1 = supports read cache commands bit 0 1 = supports page cache program command 10-31 reserved (0) manufacturer information block 32-43 m device manufacturer (12 ascii characters) 44-63 m device model (20 ascii characters) 64 m jedec manufacturer id 65-66 o date code 67-79 reserved (0) 80-83 m number of data bytes per page 84-85 m number of spare bytes per page 86-89 m number of data bytes per partial page 90-91 m number of spare bytes per partial page 92-95 m number of pages per block
nand04g-b2d, nand08g-bxc device operations 41/69 memory organization block 96-99 m number of blocks per logical unit (lun) 100 m number of logical units (luns) 101 m number of address cycles bit 4 to bit 7 column address cycles bit 0 to bit 3 row address cycles 102 m number of bits per cell 103-104 m bad blocks maximum per lun 105-106 m block endurance 107 m guaranteed valid blocks at beginning of target 108-109 m block endurance for guaranteed valid blocks 110 m number of programs per page 111 m partial programming attributes bit 5 to bit 7 reserved 4 1 = partial page layout is partial page data followed by partial page spare bit 1 to bit 3 reserved 0 1 = partial page programming has constraints 112 m number of bits ecc correctability 113 m number of interleaved address bits bit 4 to bit 7 reserved (0) bit 0 to bit 3 number of interleaved address bits 114 o interleaved operation attributes bit 4 to bit 7 reserved (0) bit 3 address restrictions for program cache bit 2 1 = program cache supported bit 1 1 = no block address restrictions bit 0 overlapped/concurrent interleaving support 115-127 reserved (0) 128 m i/o pin capacitance table 21. parameter page data structure (continued) byte o/m (1) description
device operations nand 04g-b2d, nand08g-bxc 42/69 electrical parameters block 129-130 m timing mode support bit 6 to bit 15 reserved (0) bit 5 1 = supports timing mode 5 bit 4 1 = supports timing mode 4 bit 3 1 = supports timing mode 3 bit 2 1 = supports timing mode 2 bit 1 1 = supports timing mode 1 bit 0 1 = supports timing mode 0, shall be 1 131-132 o program cache timing mode support bit 6 to bit 15 reserved (0) bit 5 1 = supports timing mode 5 bit 4 1 = supports timing mode 4 bit 3 1 = supports timing mode 3 bit 2 1 = supports timing mode 2 bit 1 1 = supports timing mode 1 bit 0 1 = supports timing mode 0 133-134 m t prog maximum page program time (s) 135-136 m t bers maximum block erase time (s) 137-138 m t r maximum page read time (s) 139-163 m reserved (0) vendor block 164-165 m vendor specific revision number 166-253 m vendor specific 254-255 m integrity crc red. param. pages 256-511 m value of bytes 0-255 512-767 m value of bytes 0-255 768+ o additional redundant parameter pages 1. o = optional, m = mandatory table 21. parameter page data structure (continued) byte o/m (1) description
nand04g-b2d, nand08g-bxc concurrent operations and extended read status 43/69 7 concurrent operations and extended read status the nand08g-bxc devices are composed of two 4-gbit dice stacked together. this configuration allows the devices to support concurrent operations, which means that while performing an operation in one die (erase, read, program, etc.), another operation is possible in the other die. the standard read status register operation returns the status of the nand08g-bxc device. to provide information on each 4-gbit die, the nand08g-bxc devices feature an extended read status register command that independently checks the status of each nand04g-b2d. the following steps are required to perform concurrent operations: 1. select one of the two dice by setting the most significant address bit a30 to ?0? or ?1?. 2. execute one operation on this die. 3. launch a concurrent operation on the other die. 4. check the status of these operations by performing an extended read status register operation. all combinations of operations are possible except read while read. this is due to the fact that the input/output bus is common to both dice. refer to ta b l e 2 2 for the description of the extended read status register command sequence, and to ta b l e 1 4 . for the definition of the status register bits. 8 data protection the devices feature a write protect, wp , pin, which can be used to protect the device against program and erase operations. it is recommended to keep wp at v il during power- up and power-down. table 22. extended read status register commands command address range 1 bus write cycle read 1st die status address 0x3fffffff f2h read 2nd die status 0x3fffffff < address 0x7ffffff f3h
software algorithms nand 04g-b2d, nand08g-bxc 44/69 9 software algorithms this section provides information on the software algorithms that st recommends implementing to manage the bad blocks and extend the lifetime of the nand device. nand flash memories are programmed and erased by fowler-nordheim tunnelling using high voltage. exposing the device to high voltage for extended periods damages the oxide layer. to extend the number of program and erase cycles and increase the data retention, the: number of program and erase cycles is limited (see table 24: program erase times and program erase endurance cycles for the values) implementation of a garbage collection, a wear-leveling algorithm and an error correction code is recommended. to help integrate a nand memory into an application, stmicroelectronics provides a file system os native reference software, which supports the basic commands of file management. contact the nearest stmicroelectronics sales office for more details. 9.1 bad block management devices with bad blocks have the same quality level and the same ac and dc characteristics as devices that have all valid blocks. a bad block does not affect the performance of valid blocks because it is isolated from the bit and common source lines by a select transistor. the devices are supplied with all the locations inside valid blocks erased (ffh). the bad block information is written prior to shipping. any block, where the 1st and 6th bytes or the 1st word in the spare area of the 1st page, does not contain ffh, is a bad block. the bad block information must be read before any erase is attempted as the bad block information may be erased. for the system to be able to recognize the bad blocks based on the original information, the creation of a bad block table following the flowchart shown in figure 21: bad block management flowchart is recommended.
nand04g-b2d, nand08g-bxc software algorithms 45/69 9.2 nand flash memory failure modes over the lifetime of the device bad blocks may develop. to implement a highly reliable system, the possible failure modes must be considered. program/erase failure in this case, the block has to be replaced by copying the data to a valid block. these additional bad blocks can be identified because attempts to program or erase them gives errors in the status register. as the failure of a page program operation does not affect the data in other pages in the same block, the block can be replaced by reprogramming the current data and copying the rest of the replaced block to an available valid block. the copy back program command can be used to copy the data to a valid block. see section 6.5: copy back program for more details. read failure in this case, ecc correction must be implemented. to efficiently use the memory space, the recovery of a single-bit error in read by ecc, without replacing the whole block, is recommended. refer to table 23: block failure for the recommended procedure to follow if an error occurs during an operation. figure 21. bad block management flowchart table 23. block failure operation procedure erase block replacement program block replacement or ecc read ecc ai07588c start end no yes yes no block address = block 0 data = ffh? last block? increment block address update bad block table
software algorithms nand 04g-b2d, nand08g-bxc 46/69 9.3 garbage collection when a data page needs to be modified, it is faster to write to the first available page, resulting in the previous page being marked as invalid. after several updates it is necessary to remove invalid pages to free memory space. to free this memory space and allow further program operations, the implementation of a garbage collection algorithm is recommended. in garbage collection software, the valid pages are copied into a free area and the block containing the invalid pages is erased as show in figure 22 . figure 22. garbage collection 9.4 wear-leveling algorithm for write-intensive applications, the implementation of a wear-leveling algorithm is recommended to monitor and spread the number of write cycles per block. in memories that do not use a wear-leveling algorithm, not all blocks get used at the same rate. the wear-leveling algorithm ensures that equal use is made of all the available write cycles for each block. there are two wear-leveling levels: first level wear-leveling, where new data is programmed to the free blocks that have had the fewest write cycles. second level wear-leveling, where long-lived data is copied to another block so that the original block can be used for more frequently-changed data. the second level wear-leveling is triggered when the difference between the maximum and the minimum number of write cycles per block reaches a specific threshold. valid page invalid page free page (erased) old area ai07599b new area (after gc)
nand04g-b2d, nand08g-bxc software algorithms 47/69 9.5 error correction code an ecc can be implemented in the nand flash memories to identify and correct errors in the data. for every 2048 bits in the device, the implementation of 22 bits of ecc (16 bits for line parity plus 6 bits for column parity) is recommended. figure 23. error detection new ecc generated during read xor previous ecc with new ecc all results = zero? 22 bit data = 0 yes 11 bit data = 1 no 1 bit data = 1 correctable error ecc error no error ai08332 >1 bit = zero? yes no
program and erase times and endura nce cycles nand04g- b2d, nand08g-bxc 48/69 10 program and erase times and endurance cycles the program and erase times and the number of program/erase cycles per block are shown in ta b l e 2 4 . table 24. program erase times and program erase endurance cycles parameters nand flash unit min typ max page program/multiplane program time 200 700 s block erase/multiplane erase time 1.5 2ms multiplane program time (1.8 v) 250 800 s multiplane erase (1.8 v) 2 2.5 ms multiplane program busy time (t ipbsy )0.51s multiplane erase busy time (t iebsy )0.51s cache read busy time (t rcbsy ) 3 t r s program/erase cycles per block (with ecc) 100 000 cycles data retention 10 years
nand04g-b2d, nand08g-b xc maximum ratings 49/69 11 maximum ratings stressing the device above the ratings listed in table 25: absolute maximum ratings may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not imp lied. exposure to absolute ma ximum rating conditions for extended periods may affect device reliabilit y. refer to the stmicroelectronics sure program and other relevant quality documents for more information. table 25. absolute maximum ratings symbol parameter value unit min max t bias temperature under bias ? 50 125 c t stg storage temperature ? 65 150 c v io (1) 1. minimum voltage may undershoot to ?2 v for less t han 20 ns during transitions on input and i/o pins. maximum voltage may overshoot to v dd + 2 v for less than 20 ns dur ing transitions on i/o pins. input or output voltage ? 0.6 4.6 v v dd supply voltage ? 0.6 4.6 v
dc and ac parameters nand04g-b2d, nand08g-bxc 50/69 12 dc and ac parameters this section summarizes the operating and measurement conditions, and the dc and ac characteristics of the devices. the parameters in the following dc and ac characteristics tables are derived from tests performed under the measurement conditions summarized in ta bl e 2 6 . designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parameters. table 26. operating and ac measurement conditions parameter nand flash units min max supply voltage (v dd )2.7 3.6v ambient temperature (t a ) grade 1 0 70 c grade 6 ?40 85 c load capacitance (c l ) (1 ttl gate and c l ) 1.8 v device 30 pf 3.0 v device 50 pf input pulses voltages 0 v dd v input and output timing ref. voltages v dd /2 v output circuit resistor r ref 8.35 k ? input rise and fall times 5 ns table 27. capacitance (1) 1. t a = 25c, f = 1mhz. c in and c i/o are not 100% tested. symbol parameter test condition typ max unit c in input capacitance v in = 0v 10 pf c i/o input/output capacitance (2) 2. input/output capacitances double in stacked devices. v il = 0v 10 pf
nand04g-b2d, nand08g-bxc dc and ac parameters 51/69 figure 24. equivalent testing circuit for ac characteristics measurement ai11085 nand flash c l 2r ref v dd 2r ref gnd gnd table 28. dc characteristics (1.8 v devices) symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e =v il, i out = 0 ma -1020ma i dd2 program - - 10 20 ma i dd3 erase - - 10 20 ma i dd5 standby current (cmos (1) ) e =v dd -0.2, wp =0/v dd - 10 50 a i li input leakage current (1) v in = 0 to v dd max - - 10 a i lo output leakage current (1) v out = 0 to v dd max - - 10 a v ih input high voltage - 0.8 * v dd - v dd + 0.3 v v il input low voltage - -0.3 - 0.2 * v dd v v oh output high voltage level i oh = -100 a v dd - 0.1 - - v v ol output low voltage level i ol = 100 a - - 0.1 v i ol (rb ) output low current (rb ) v ol = 0.1 v 3 - 4 ma v lko v dd supply voltage (erase and program lockout) - - - 1.2 v 1. leakage current and standby current double in stacked devices.
dc and ac parameters nand04g-b2d, nand08g-bxc 52/69 table 29. dc characteristics (3 v devices) symbol parameter test conditions min typ max unit i dd1 operating current sequential read t rlrl minimum e = v il, i out = 0 ma -1530ma i dd2 program - - 15 30 ma i dd3 erase - - 15 30 ma i dd4 standby current (ttl) (1) e = v ih , wp = 0/v dd 1 ma i dd5 standby current (cmos) (1) e = v dd -0.2, wp = 0/v dd - 10 50 a i li input leakage current (1) v in = 0 to v dd max - - 10 a i lo output leakage current (1) v out = 0 to v dd max - - 10 a v ih input high voltage - 0.8 v dd - v dd +0.3 v v il input low voltage - -0.3 - 0.2 v dd v v oh output high voltage level i oh = -400 a 2.4 - - v v ol output low voltage level i ol = 2.1 ma - - 0.4 v i ol (rb ) output low current (rb ) v ol = 0.4 v 8 - 10 ma v lko v dd supply voltage (erase and program lockout) - - - 1.8 v 1. leakage current and standby curr ent double in stacked devices. table 30. ac characteristics for command, address, data input symbol alt. symbol parameter 1.8 v 3 v unit t allwh t als address latch low to write enable high al setup time min 25 12 ns t alhwh address latch high to write enable high t clhwh t cls command latch high to write enable high cl setup time min 25 12 ns t cllwh command latch low to write enable high t dvwh t ds data valid to write enable high data setup time min 20 12 ns t elwh t cs chip enable low to write enable high e setup time min 35 20 ns t whalh t alh write enable high to address latch high al hold time min 10 5 ns t whclh t clh write enable high to command latch high cl hold time min 10 5 ns t whcll write enable high to command latch low t whdx t dh write enable high to data transition data hold time min 10 5 ns t wheh t ch write enable high to chip enable high e hold time min 10 5 ns t whwl t wh write enable high to write enable low w high hold time min 15 10 ns t wlwh t wp write enable low to write enable high w pulse width min 25 12 ns t wlwl t wc write enable low to write enable low write cycle time min 45 25 ns
nand04g-b2d, nand08g-bxc dc and ac parameters 53/69 table 31. ac characteristics for operations (1) symbol alt. symbol parameter 1.8 v 3 v unit t allrl1 t ar address latch low to read enable low read electronic signature min 10 10 ns t allrl2 read cycle min 10 10 ns t bhrl t rr ready/busy high to read enable low min 20 20 ns t blbh1 ready/busy low to ready/busy high read busy time max 25 25 s t blbh2 t prog program busy time max 700 700 s t blbh3 t bers erase busy time max 2 2 ms t blbh4 t rst reset busy time, during ready max 5 5 s reset busy time, during read max 5 5 s reset busy time, during program max 10 10 s reset busy time, during erase max 500 500 s t cllrl t clr command latch low to read enable low min 10 10 ns t dzrl t ir data hi-z to read enable low min 0 0 ns t ehqz t chz chip enable high to output hi-z max 30 30 ns t ehalx t csd chip enable high to address latch ?don?t care? min 10 10 ns t ehclx chip enable high to command latch ?don?t care? t rhqz t rhz read enable high to output hi-z max 100 100 ns t elqv t cea chip enable low to output valid max 45 25 ns t rhrl t reh read enable high to read enable low read enable high hold time min 15 10 ns t ehqx t coh chip enable high to output hold min 15 15 ns t rhqx t rhoh read enable high to output hold min 15 15 ns t rlqx t rloh read enable low to output hold (edo mode) min 5 5 ns t rlrh t rp read enable low to read enable high read enable pulse width min 25 12 ns t rlrl t rc read enable low to read enable low read cycle time min 45 25 ns t rlqv t rea read enable low to output valid read enable access time max 30 20 ns read es access time (2) t whbh t r write enable high to ready/busy high read busy time max 25 25 s t whbl t wb write enable high to ready/busy low max 100 100 ns t whrl t whr write enable high to read enable low min 60 60 ns t rhwl t rhw read enable high to write enable low min 100 100 ns
dc and ac parameters nand04g-b2d, nand08g-bxc 54/69 figure 25. command latch ac waveforms t whwh t adl (3) last address latched to data loading time during program operations min 100 70 ns t vhwh t vlwh t ww (4) write protection time min 100 100 ns 1. the time to ready depends on the value of the pul l-up resistor tied to the ready/busy pin. see figure 41 , figure 42 and figure 43 . 2. es = electronic signature. 3. t adl is the time from w rising edge during the fi nal address cycle to w rising edge during t he first data cycle. 4. during a program/erase enable operation, t ww is the delay from wp high to w high. during a program/erase disable operation, t ww is the delay from wp low to w high. table 31. ac characteristics for operations (1) (continued) ai12470b cl e w al i/o tclhwh telwh twhcll twheh twlwh tallwh twhalh command tdvwh twhdx (cl setup time) (cl hold time) (data setup time) (data hold time) (alsetup time) (al hold time) h(e setup time) (e hold time)
nand04g-b2d, nand08g-bxc dc and ac parameters 55/69 figure 26. address latch ac waveforms figure 27. data input latch ac waveforms 1. the last data input is the 2112th. ai12471 cl e w al i/o twlwh telwh twlwl tcllwh twhwl talhwh tdvwh twlwl twlwl twlwh twlwh twlwh twhwl twhwl twhdx twhall tdvwh twhdx tdvwh twhdx tdvwh twhdx twhall adrress cycle 1 twhall (al setup time) (al hold time) adrress cycle 4 adrress cycle 3 adrress cycle 2 (cl setup time) (data setup time) (data hold time) (e setup time) adrress cycle 5 twlwl twlwh tdvwh twhdx twhwl twhall twhclh cl e al w i/o tallwh twlwl twlwh twheh twlwh twlwh data in 0 data in 1 data in last tdvwh twhdx tdvwh twhdx tdvwh twhdx ai12472 (data setup time) (data hold time) (alsetup time) (cl hold time) (e hold time)
dc and ac parameters nand04g-b2d, nand08g-bxc 56/69 figure 28. sequential data output after read ac waveforms 1. cl = low, al = low, w = high. 2. t rhqx is applicable for frequencies lower than 33mhz (i.e. t rlrl higher than 30ns). figure 29. sequential data output after read ac waveforms (edo mode) 1. in edo mode, cl and al are low, v il , and w is high, v ih . 2. t rlqx is applicable for frequencies high than 33 mhz (i.e. t rlrl lower than 30 ns). e ai13174 r i/o rb trlrl trlqv trhrl trlqv data out data out data out trhqz tbhrl trlqv trhqz tehqz (read cycle time) (r accesstime) (r high holdtime) tehqx trhqx (2) e ai13175 r i/o rb trlrl trlqv trhrl trlqv data out data out data out tbhrl trhqz tehqz (r accesstime) tehqx trhqx (2) trlrh telqv trlqx
nand04g-b2d, nand08g-bxc dc and ac parameters 57/69 figure 30. read status register or read edc status register ac waveform figure 31. read status enhanced waveform telwh tdvwh status register output 70h or 7bh cl e w r i/o tclhwh twhdx twlwh twhcll tcllrl tdzrl trlqv tehqx trhqx twhrl telqv twheh ai13177 (data setup time) (data hold time) tehqz trhqz cl i/o0-7 78h ai14408 w al r address 1 address 3 address 2 status register output
dc and ac parameters nand04g-b2d, nand08g-bxc 58/69 figure 32. read electronic signature ac waveform 1. refer to table 16 for the values of the manufacturer and device codes, and to table 17 , table 18 , and table 19 for the information contained in byte 3, byte 4, and byte 5. figure 33. read onfi signature waveform 90h 00h man. code device code cl e w al r i/o trlqv read electronic signature command 1st cycle address ai13178 (read es access time) tallrl1 byte4 byte3 byte1 byte2 see note.1 byte5 90h 20h cl e w al r i/o trlqv read electronic signature command 1st cycle address ai13178b (read es access time) tallrl1 49h 46h 4fh 4eh xxh
nand04g-b2d, nand08g-bxc dc and ac parameters 59/69 figure 34. page read operation ac waveform cl e w al r i/o rb twlwl twhbl tallrl2 00h data n data n+1 data n+2 data last twhbh trlrl tehqz trhqz ai12474b busy command code address n input data output from address n to last byte or word in page add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (read cycle time) trlrh tblbh1 30h add.n cycle 5 tehalx tehclx
dc and ac parameters nand04g-b2d, nand08g-bxc 60/69 figure 35. page program ac waveform cl e w al r i/o rb sr0 ai12475b n last 10h 70h 80h page program setup code confirm code read status register twlwl twlwl twlwl twhbl tblbh2 page program address input data input add.n cycle 1 add.n cycle 4 add.n cycle 3 add.n cycle 2 (write cycle time) (program busy time) add.n cycle 5 twhwh twhrl
nand04g-b2d, nand08g-bxc dc and ac parameters 61/69 figure 36. block erase ac waveform figure 37. reset ac waveform d0h 60h sr0 70h ai08038c twhbl twlwl tblbh3 block erase setup command block erase cl e w al r i/o rb confirm code read status register block address input (erase busy time) (write cycle time) add. cycle 1 add. cycle 3 add. cycle 2 twhrl w r i/o rb tblbh4 al cl ffh ai08043 (reset busy time)
dc and ac parameters nand04g-b2d, nand08g-bxc 62/69 figure 38. program/erase enable waveform figure 39. program/erase disable waveform figure 40. read parameter page waveform w rb tvhwh ai12477 wp i/o 80h 10h w rb tvlwh ai12478 wp i/o 80h 10h high ech 00h cl w al r i/o0-7 ai14409 p1 1 p0 1 p1 0 ... ... p0 0 tblbh1 r/b
nand04g-b2d, nand08g-bxc dc and ac parameters 63/69 12.1 ready/busy signal electrical characteristics figure 42 , figure 41 and figure 43 show the electrical charac teristics for the ready/busy signal. the value required for the resistor r p can be calculated using the following equation: this is an example for 3 v devices: where i l is the sum of the input currents of all the devices tied to the ready/busy signal. r p max is determined by the maximum value of t r . figure 41. ready/busy ac waveform figure 42. ready/busy load circuit r p min v ddmax v olmax ? () i ol i l + ------------------------------------------------------------- = r p min 3.2v 8ma i l + --------------------------- = ai07564b busy v oh ready v dd v ol t f t r ai07563b r p v dd v ss rb device open drain output ibusy
dc and ac parameters nand04g-b2d, nand08g-bxc 64/69 figure 43. resistor value versus waveform timings for ready/busy signal 1. t = 25c. 12.2 data protection the st nand devices aredesigned to guarantee data protection during power transitions. a v dd detection circuit disables all nand operations, if v dd is below the v lko threshold. in the v dd range from v lko to the lower limit of nominal range, the wp pin should be kept low (v il ) to guarantee hardware protection during power transitions as shown in the below figure. figure 44. data protection ai1247 6 t r t f ibusy r p (k ?) 12 34 50 150 100 1 2 3 ibusy (ma) 2.4 1.2 0.8 0.6 50 100 150 200 1.8 1.8 1.8 1.8 0 200 4 v dd = 3.3 v, c l = 50 pf t r , t f (ns) ai11086 v lko v dd w nominal range locked locked
nand04g-b2d, nand08g-b xc package mechanical 65/69 13 package mechanical figure 45. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package outline 1. drawing is not to scale. tsop-g b e die c l a1 e1 e a a2 1 24 48 25 d1 l1 cp table 32. tsop48 - 48 lead plastic thin small outline, 12 x 20 mm, package mechanical data symbol millimeters inches typ min max typ min max a 1.200 0.0472 a1 0.100 0.050 0.150 0.0039 0.0020 0.0059 a2 1.000 0.950 1.050 0.0394 0.0374 0.0413 b 0.220 0.170 0.270 0.0087 0.0067 0.0106 c 0.100 0.210 0.0039 0.0083 cp 0.080 0.0031 d1 12.000 11.900 12.100 0.4724 0.4685 0.4764 e 20.000 19.800 20.200 0.7874 0.7795 0.7953 e1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 ? ? 0.0197 ? l 0.600 0.500 0.700 0.0236 0.0197 0.0276 l1 0.800 0.0315 a 305305
package mechanical nand 04g-b2d, nand08g-bxc 66/69 figure 46. lga52 12 x 17 mm, 1 mm pitch , package outline e1 e2 d1 d2 eb2 lga-9g ball "a1" e d b1 e ee1 a2 a ddd fd fd1 fe fe1 table 33. lga52 12 x 17 mm, 1 mm pitch , package mechanical data symbol millimeters inches typ min max typ min max a 0.650 0.0256 a2 0.650 0.0256 b1 0.700 0.650 0.750 0.0276 0.0256 0.0295 b2 1.000 0.950 1.050 0.0394 0.0374 0.0413 d 12.000 11.900 12.100 0.4724 0.4685 0.4764 d1 6.000 0.2362 d2 10.000 0.3937 ddd 0.100 0.0039 e 17.000 16.900 17.100 0.6693 0.6654 0.6732 e1 12.000 0.4724 e2 13.000 0.5118 e 1.000 ? ? 0.0394 ? ? ee1 2.000 ? ? 0.0787 ? ? fd 3.000 0.1181 fd1 1.000 0.0394 fe 2.500 0.0984 fe1 2.000 0.0787
nand04g-b2d, nand08g-b xc part numbering 67/69 14 part numbering devices are shipped from the factory with the memory content bits, in valid blocks, erased to ?1?. for further information on any aspect of this device, please contact your nearest st sales office. table 34. ordering information scheme example: nand04gw3b2d n 6 e device type nand flash memory density 04 g = 4 gb 08 g = 8 gb operating voltage w = v dd = 2.7 to 3.6 v r = v dd = 1.7 to 1.95 v bus width 3 = x8 4 = x16 (1) 1. x16 organization only av ailable for mcp products family identifier b = 2112 byte page device options 2 = chip enable ?don't care? enabled 4 = chip enable ?don?t care? enabled with dual interface product version c= third version (nand08g-bxc) d = fourth version (nand04g-b2d) package n = tsop48 12 x 20 mm zl = lga52 12 x 17 mm temperature range 1 = 0 to 70 c 6 = ?40 to 85 c option e = ecopack package, standard packing f = ecopack package, tape and reel packing
revision hist ory nand04g-b2d, nand08g-bxc 68/69 15 revision history table 35. document revision history date revision changes 22-june-2007 1 initial release. 17-sep-2007 2 added the part numbers nand08gr3b4c, nand08gw3b4c, therefore referring to the 8 gbit devices as the nand08g-bxc. modified all data throughout this document to reflect the addition of these part numbers, namely: ? ta bl e 1 , ta bl e 2 , ta bl e 6 , and ta b l e 3 4 . ? added figure 5: lga52 connections for the nand08g-b4c devices . changed v lko value in ta b l e 2 8 from 1.1 to 1.2.
nand04g-b2d, nand08g-bxc 69/69 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a parti cular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by an authorized st representative, st products are not recommended, authorized or warranted for use in milita ry, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or registered trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2007 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com

▲Up To Search▲

Price & Availability of NAND04GR3B2DZL1F

	To Download NAND04GR3B2DZL1F Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .